This invention relates to a frequency divider that receives an input clock signal and generates an output clock signal having a lower frequency. More particularly, it relates to an improved frequency divider with reduced clock skew.
Frequency dividers are extensively used in semiconductor integrated circuits, but existing frequency dividers tend to generate a large clock skew; that is, transitions in the output clock signal lag transitions in the input clock signal by a large amount. Clock skew can cause major timing difficulties, particularly when both the input and output clock signals are used for timing purposes.